An RSA Encryption Hardware Algorithm using a Single DSP Block and a Single Block RAM on the FPGA

Algorithm 1 ENC : encryption of a single block

Efficient Hardware Implementation of the Lightweight Block Encryption Algorithm LEA

Recently, due to the advent of resource-constrained trends, such as smartphones and smart devices, the computing environment is changing. Because our daily life is deeply intertwined with ubiquitous networks, the importance of security is growing. A lightweight encryption algorithm is essential for secure communication between these kinds of resource-constrained devices, and many researchers ha...

The Parallel FDFM Processor Core Approach for CRT-based RSA Decryption

One of the key points of success in high performance computation using an FPGA is the efficient usage of DSP slices and block RAMs in it. This paper presents a FDFM (Few DSP slices and Few block RAMs) processor core approach for implementing RSA encryption. In our approach, an efficient hardware algorithm for Chinese Remainder Theorem (CRT) based RSA decryption using Montgomery multiplication a...

Scalable RSA Processor in Reconfigurable Hardware - a SoC Building Block

The paper introduces a scalable programmable RSA cryptographic processor implemented as IP core in Field Programmable Devices (FPD). The processor is built on three main blocks – an embedded standard microcontroller, a scalable Montgomery Multiplication unit and simple vector adder unit. All blocks are implemented in VHDL as parameterized modules. The IP core is developed as a System on a Chip ...

Logistic map as a block encryption algorithm

We discuss the relationship between cryptography and chaos theory, and similarities of their crucial concepts such as mixing property and sensitivity to changes in initial conditions and parameters. A systematic procedure for design of encryption algorithms based on chaotic maps is suggested. We present an example based on logistic map.  2001 Elsevier Science B.V. All rights reserved.